Synchronous semiconductor memory devices such as synchronous DRAM (Dynamic Random Access Memory) are widely employed in the main memory of personal computers and the like. Synchronous semiconductor memory devices are a type of memory wherein data is input and output synchronously with a clock signal that is provided from a controller. The clock frequency has increased with each successive year in order to meet demands over the past several years for higher speeds.
Meanwhile, a dramatic increase has occurred especially in the demand for lower power consumption in mobile device applications and the like. However, as the clock frequency increases, the power consumption also increases. Therefore, various designs have been presented in recent synchronous DRAMs to simultaneously achieve high speed and low power consumption.
One technique for achieving lower power consumption is an operation mode called “power-down mode.” Power-down mode is a technique wherein the input buffer is stopped to disable the command input from a controller, thereby reducing the power consumed during the period when the DRAM is not accessed. See Japanese Patent Application Laid Open No. H9-69285.
Power-down mode is usually initiated by changing the clock enable signal CKE from a high level to a low level after a data transfer operation sequence is complete; e.g., after a read operation sequence is performed in response to a read command. However, a specification called “early power-down” has been proposed over the past several years, wherein the clock enable signal CKE is changed from a high level to a low level before the read operation, write operation, or other operation sequence is complete. A semiconductor memory device capable of receiving early power-down will automatically enter power-down mode after a read operation, write operation, or other operation sequence is completed once the clock enable signal CKE is changed to a low level while the read operation or write operation is executed by the DRAM core.
In a semiconductor memory device capable of receiving early power-down, accordingly, the clock enable signal CKE is changed to a low level while a read operation or write operation is being executed by the DRAM core. For this reason, a read enable signal or write enable signal must be generated within the DRAM, thereby allowing the read operation or write operation to continue so that the DRAM core operation does not stop midway through. When the read operation or write operation is completed, the read enable signal or write enable signal is deactivated, and, in response, entry into power-down mode will commence.
However, most synchronous DRAMs are capable of receiving a new read command or write command while a read operation or write operation is being performed. In such cases, the operation sequence corresponding to the first received read command or write command is completed, and the subsequently received operation corresponding to the read command or write command is then initiated. For this reason, a detection circuit for detecting whether all read operations or write operations have been completed at a given time is necessary in order to enable such synchronous DRAMs to receive early power-down.
This problem arises not only with synchronous DRAM, but also in CPUs with on-board cache memory and other devices wherein it is necessary to detect the completion of read operations, write operations, and other data transfer operations.